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2+ Synopsys Jobs in India

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Smart Soc Solutions

at Smart Soc Solutions

6 recruiters
Sayantika Majumdar
Posted by Sayantika Majumdar
Bengaluru (Bangalore), Hyderabad
2 - 20 yrs
₹5L - ₹50L / yr
Physical Design
Static timing analysis
Application Specific Integrated Circuit (ASIC)
Floorplan Manager
Extraction
+1 more

Physical Design - JD

Experience: 2-20 yrs
1.Strong background of ASIC Physical Design: Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.                          
2.Hands-on experience on technology nodes like 7nm, 14nm, 10nm.
3.Good knowledge of EDA tools from Synopsys , Cadence and Mentor              
4.Hands-on experience in floor planning, placement optimizations, CTS and routing.                                  
5.Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS)

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MNC

MNC

Agency job
via CRB Tech Solution by Sneha Bhonde
Bengaluru (Bangalore), Ahmedabad, Noida, NCR (Delhi | Gurgaon | Noida)
6 - 10 yrs
₹1L - ₹10L / yr
Semiconductors
Application Specific Integrated Circuit (ASIC)
Synopsys
Floor Planning
GDS
+1 more

Dear Connections,

Roles & Responsibility:-
Should execute block level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.

 

Physical Design Implementation on advanced technology nodes like 28nm, 20nm for block level implementation. Good understanding on low power concepts. Good understanding on top level physical design, partitioning and timing constraints, IR Drop.

Candidate should be from semiconductor/'ASIC industry
Excellent knowledge on GDS To Netlift

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