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6+ VLSI Jobs in India

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Samniya Techsys
Jaganmohan Karla
Posted by Jaganmohan Karla
Remote only
5 - 7 yrs
₹1L - ₹35L / yr
VLSI
RTL
EMIR

Job Description :

 

Own partition floorplanning for optimizing blocks for Power, Performance and Area.

Own execution from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.

Have close collaboration with RTL team to help drive and resolve design issues related to block closure.

Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.

Implement robust clock distribution solutions using appropriate methods that meet design requirements.

Make good independent technical trade-offs between power, area, and timing (PPA)

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Acceptance Re Innovation Technology
Sibasish Mishra
Posted by Sibasish Mishra
Bengaluru (Bangalore)
0 - 7 yrs
₹10000 - ₹13000 / mo
Embedded Systems
Embedded C
Embedded C++
Internet of Things (IOT)
Xilinx
+3 more

StartUp engaged in inventing and innovating Smart Energy Meters and related Technologies (OEM) requires Embedded Engineers. Following re-innovation principle and Technology First direction, we design Technologies to deliver our Vision of the highest Quality Products and Technologies. The candidate's responsibilities include IoT (COSEM/DLMS), technology integration. Required skills include Embedded C and C++ and knowledge of Electrical and Electronics.

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5G Test Bed IIT Hyderabad
Srinivasa Rao  K V N
Posted by Srinivasa Rao K V N
Hyderabad, Sangareddy
1 - 2 yrs
₹4L - ₹7L / yr
Linux/Unix
Analog And Digital Circuits
Mixed-signal integrated circuit
Application Specific Integrated Circuit (ASIC)
VLSI
+2 more

Job Title: Project Associate - Mixed Signal Design Profile
Industry: Wireless communication, 5G
Organization: 5G TestBed-IIT Hyderabad- Hyderabad

Job Description
Work Profile:
· Work on development of custom Analog circuit boards for applications related to RF, interfaces etc.
· Implement new features and bug fixes
· Verify analog/mixed-signal integrated circuits
· Develop test cases to verify new features and bug fixes
· Review and update the user manuals for software tools.
· Supporting digital modelling of analog circuits for mixed-signal verification
· Creating design specifications and circuit schematics
· Work both independently and in a team environment, with the opportunity to provide technical leadership to other members of the engineering team
· Create and/or modify specification documents detailing system design and enhancements to meet marketing requirements
· Collaborate with others in the creation of technical reports, whitepapers, and user documentation

Requisites:
· EE/EEE/ECE graduate, undergraduate degree from reputed Tier 1 or Tier 2 colleges .
· Strong knowledge of analog integrated circuit design fundamentals
· Proven experience taking designs from concept to production
· Experience in analog/mixed-signal IC design & verification
· Understanding of BJT, CMOS and Op-Amp technologies.
· Good understanding of analog/mixed-signal design flows (Cadence, Synopsys)
· Transistor and system level simulation skills
· Discrete time and continuous time signal processing skills
· Strong lab and silicon validation skills
· Verilog based digital design and test bench development, is a plus
· Strong communication skills, both written and verbal
About us:
For more details please visit: http://5g.iith.ac.in/
IIT Hyderabad in collaboration with top Indian institutes including IITM, CEWiT, IITD, IITK, IISC and SAMEER is building the largest 5G testbed of the country, with the support of Department of Telecommunications (DoT) Govt. of India. This project will create a 5G prototype and testing platform that will be developed under the guidance of IIT-H faculty.
The project will deliver an end-to-end 5G testbed comprising 5G BS and UE nodes that support enhanced mobile broadband (eMBB), Ultra low latency communication (URLLC), and massive MTC including NB IoT services. The operating frequently includes both sub 6 GHz and mmwave frequencies. The system will exceed IMT 2020 5G performance requirements including Low Mobility Large Cell (i.e.., LMLC) targets introduced by India at ITU.
The 'Indigenous 5G Testbed' project is a long-term effort with a team of 100+ researchers/engineers based out of IIT-H campus.


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Espressif Systems India Pvt Ltd
Remote, Pune
3 - 10 yrs
₹15L - ₹30L / yr
Verilog
skill iconC
SystemVerilog
VMM
UVM
+3 more
Digital Verification Engineer About Company: Espressif Systems is a multinational, fabless semiconductor company established in 2008, with headquarters in Shanghai and offices in Greater China, India and Europe. We have a passionate team of engineers and scientists from all over the world, focused on developing cutting-edge WiFi-and-Bluetooth, low-power, IoT solutions. Among our popular products are the ESP8266 and ESP32 series of chips, modules and development boards. Job Description 1. Develop verification programs and define the verification environment according to design documentation, in order to conduct module- to chip-level verification; 2. Perform regression tests to improve verification coverage; 3. Assist the FPGA and software teams in FPGA prototype testing; 4. Collaborate with chip design engineers to find and fix any design defects; 5. Ensure the integrity of chip designs by supervising the design department when building verifiable design processes; 6. Carry out door-level simulation, with UPF verification methodology, to ensure successful chip tapeout. Job Prerequisites 1. Bachelor’s degree, or above, in Computer Engineering/Electronic Engineering/Communications Engineering, or other related disciplines; 2. 5+ years of work experience; 3. Familiarity with SoC and communication theory; 4. Familiarity with Verilog, proficiency in C/System Verilog verification; 5. Proficiency in Perl/Shell/Tcl scripts; 6. Experience in FPGA verification and/or chip tapeout is a plus; 7. Familiarity with VMM/UVM is a plus.
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Swedium Global Services

at Swedium Global Services

2 recruiters
harshini talla
Posted by harshini talla
SWEDEN, FINLAND
5 - 12 yrs
₹15L - ₹30L / yr
Application Specific Integrated Circuit (ASIC)
VLSI
Verilog
SV
UVM
+1 more
Job description: A strong experience in block design and IP verification within digital ASIC. Good experience in SystemVerilog and UVM Methodology based verification Minimum of 5+ Years of ASIC Verification experience Good command on English both in written and spoken, Swedish language knowledge is an advantage You should have Positive attitude, social skills, a desire to help team members, structured way of working and an eye for quality work. You enjoy working both independently and in a small diverse and you are focused on reaching result on time. The work will be carried out in a cross functional team using Scrum/Agile ways of working Skills Required: Design verification Skills Miscellaneous tasks in connection to the block design Verification planning Verification specification Verification environment (creation/adaptation/maintenance). Verification documentation Test case creation Usage of reference models Constrained random testing Creation of Coverage matrix Experienced in WCDMA, GSM and/or LTE systems.
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Alten calsoft labs

d

at Alten calsoft labs

3 recruiters
Alok Tiwari
Posted by Alok Tiwari
Bengaluru (Bangalore), Bengaluru (Bangalore)
3 - 15 yrs
₹5L - ₹24L / yr
uvm
systemverilog
rtl
semiconductor
cdc
+3 more
ALTEN Calsoft Labs expertise in VLSI services can transfer your product ideas into cost-effective System on Chip (SoC) designs for Networking, Mobile Multimedia and Consumer Electronics solutions with a faster time to market. Some of the key highlights of our Semiconductor Practice include - Multiple engagements with Tier-1 silicon vendors and fabless semiconductor companies from Spec-to-Netlist Focus on latest verification methodologies - OVM, VMM and UVM Verification & validation experience of complex SOC designs up to 28 nm process technology Expertise in implementing complex ASICs in 130nm, 90nm, 65nm & 40nm
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